In the manufacture of very large scale integrated circuit chips, the manufacturing steps include the initial step of creating a detailed circuit diagram of the system which is to be manufactured on the integrated circuit chip. After the circuit diagram has been designed, different photographic masks are prepared for the implementation of the circuit diagram into physical form on the chip. Different steps in the manufacturing process use these masks for effecting the doping of the silicon crystal forming the chip. The die size of a typical chip, including many thousands of components, is one-half inch by one half inch. Because of the large number of components, it is possible for errors to be made, either in the original circuit design or in the various masks which are employed to incorporate that circuit onto the chip through the manufacturing process.
To ensure that the manufactured chip performs in accordance with the original intended design, test operations of the chip typically are undertaken prior to the sale of the chip to customer. Even so, an occasional problem exists, in which chips tend to draw excess current when they are installed into an end-use system. Excessive current draw can be a significant problem for chips which are used in portable computers and the like, since the excessive current draw depletes the useful battery life of such portable devices sooner than intended. More generally, excessive current draw is often viewed as a potential reliability problem. One type of flaw which causes excessive current draw is the existence of one or more "floating nodes" on a chip when these nodes are created by design flaws in the original circuit design and/or in the manufacturing processes as a result of a flaw in one or more of the masks used during the manufacturing process. During operating tests of such chips, such "floating nodes" often are undetected, since the chips generally perform as designed, with the exception of the excessive current draw.
It has been discovered that "floating node" design flaws on a chip are often light sensitive (that is, the excessive current draw disappears in the presence or absence of light). Since integrated circuit chips typically are potted or shielded from light in their final packages, the floating node excessive current draw takes place. Even should the current draw not be inversely sensitive to light (that is, the excessive current draw disappears in the absence of light), the unstable nature of a floating node makes the future behavior of the activation unpredictable.
Accordingly, it is desirable to provide a method and apparatus for locating floating node circuit design flaws in an effective manner to pinpoint the specific areas of the chip having such floating nodes.